frequency multiplier and zero delay buffe r w194 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 march 16, 2001. rev. *c 1w194 features ? two outputs configuration options allow various multiplications of the reference frequency?refer to ta bl e 1 to determine the specific option which meets your multiplication needs available in 8-pin soic package key specifications operating voltage: ............................ 3.3v 5% or 5.0 10% operating range: .......................10 mhz < f out1 < 133 mhz absolute jitter: ......................................................... 500 ps output to output skew: .............................................. 250 ps propagation delay: ....................................................350 ps propagation delay is affected by input rise time. table 1. configuration options fbin fs0 fs1 out1 out2 out1 0 0 2 x ref ref out1 1 0 4 x ref 2 x ref out1 0 1 ref ref/2 out1 1 1 8 x ref 4 x ref out2 0 0 4 x ref 2 x ref out2 1 0 8 x ref 4 x ref out2 0 1 2 x ref ref out2 1 1 16 x ref 8 x ref block diagram pin configuration q fs0 fs1 reference fbin phase detector charge pump loop filter vco 2 output buffer out1 out2 output buffer external feedback connection to out1 or out2, not both input in out2 vdd out1 fs1 8 7 6 5 fbin in gnd fs0 1 2 3 4 soic
w194 2 overview the w194-70 is a two-output zero delay buffer and frequency multiplier. it provides an external feedback path allowing max- imum flexibility when implementing the zero delay feature. this is explained further in the sections of this data sheet titled ?how to implement zero delay,? and ?inserting other devices in feedback path.? the w194-70 is a pin-compatible upgrade of the cypress w42c70-01. the w194-70 addresses some application de- pendent problems experienced by users of the older device. pin definitions pin name pin no. pin type pin description in 2 i reference input: the output signals will be synchronized to this signal. fbin 1 i feedback input: this input must be fed by one of the outputs (out1 or out2) to ensure proper functionality. if the trace between fbin and the output pin being used for feedback is equal in length to the traces between the outputs and the signal destinations, then the signals received at the destinations will be synchronized to the ref signal input (in). out1 6 o output 1: the frequency of the signal provided by this pin is determined by the feedback signal connected to fbin, and the fs0:1 inputs (see ta b l e 1 ). out2 8 o output 2: the frequency of the signal provided by this pin is one-half of the frequency of out1. see ta b l e 1 . vdd 7 p power connections: connect to 3.3v or 5v. this pin should be bypassed with a 0.1- f decoupling capacitor. use ferrite beads to help reduce noise for optimal jitter performance. gnd 3 p ground connection: connect all grounds to the common system ground plane. fs0:1 4, 5 i function select inputs: tie to v dd (high, 1) or gnd (low, 0) as desired per ta b l e 1 . c8 g ferrite bead power supply connection v+ g c a g fs1 fs0 gnd in fbin 10 f 0.01 f 1 2 3 4 8 7 6 5 22 ? 22 ? g c9 = 0.1 f output 1 output 2 out 2 v dd out 1 figure 1. schematic/suggested layout
w194 3 how to implement zero delay typically, zero delay buffers (zdbs) are used because a de- signer wants to provide multiple copies of a clock signal in phase with each other. the whole concept behind zdbs is that the signals at the destination chips are all going high at the same time as the input to the zdb. in order to achieve this, layout must compensate for trace length between the zdb and the target devices. the method of compensation is described below. external feedback is the trait that allows for this compensation. the pll on the zdb will cause the feedback signal to be in phase with the reference signal. when laying out the board, match the trace lengths between the output being used for feedback and the fbin input to the pll. if it is desirable to either add a little delay, or slightly precede the input signal, this may also be affected by either making the trace to the fbin pin a little shorter or a little longer than the traces to the devices being clocked. inserting other devices in feedback path another nice feature available due to the external feedback is the ability to synchronize signals to the signal coming from some other device. this implementation can be applied to any device (asic, multiple output clock buffer/driver, etc.) which is put into the feedback path. referring to figure 2 , if the traces between the asic/buffer and the destination of the clock signal(s) (a) are equal in length to the trace between the buffer and the fbin pin, the signals at the destination(s) device will be driven high at the same time the reference clock provided to the zdb goes high. synchronizing the other outputs of the zdb to the outputs from the asic/buffer is more complex however, as any propagation delay from the zdb output to the asic/buffer output must be accounted for. reference signal feedback input asic/ buffer zero delay buffer a figure 2. 6 output buffer in the feedback path
w194 4 absolute maximum ratings stresses greater than those listed in this table may cause per- manent damage to the device. these represent a stress rating only. operation of the device at these or any other conditions above those specified in the operating sections of this specifi- cation is not implied. maximum conditions for extended peri- ods may affect reliability. . parameter description rating unit v dd , v in voltage on any pin with respect to gnd ?0.5 to +7.0 v t stg storage temperature ?65 to +150 c t a operating temperature 0 to +70 c t b ambient temperature under bias ?55 to +125 c p d power dissipation 0.5 w dc electrical characteristics : t a = 0c to 70c or ?40 to 85c, v dd = 3.3v 5% parameter description test condition min. typ. max. unit i dd supply current unloaded, 100 mhz 17 35 ma v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage i ol = 12 ma i ol = 8 ma 0.4 v v oh output high voltage i ol = 12 ma i ol = 8 ma 2.4 v i il input low current v in = 0v ?40 5 a i ih input high current v in = v dd 5 a dc electrical characteristics : t a = 0c to 70c or ?40 to 85c, v dd = 5v 10% parameter description test condition min. typ. max. unit i dd supply current unloaded, 100 mhz 17 35 ma v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage i ol = 12 ma i ol = 8 ma 0.4 v v oh output high voltage i ol = 12 ma i ol = 8 ma 2.4 v i il input low current v in = 0v ?80 5 a i ih input high current v in = v dd 5 a
w194 5 document #: 38-00794-*c ac electrical characteristics: t a = 0c to +70c or ?40 to 85c, v dd = 3.3v 5% parameter description test condition min. typ. max. unit f in input frequency [1] out2 = ref mhz f out output frequency out1 15-pf load [2] 10 133 mhz t r output rise time 2.0v to 0.8v, 15-pf load 3.5 ns t f output fall time 2.0v to 0.8v, 15-pf load 2.5 ns t iclkr input clock rise time [3] 10 ns t iclkf input clock fall time [3] 10 ns t pd fbin to ref skew [4, 5] measured at v dd /2 ?2 0.6 2 ns t d duty cycle 15-pf load [6] 40 50 60 % t lock pll lock time power supply stable 1.0 ms t jc jitter, cycle-to-cycle fout >30 mhz 300 ps t dc die out time [7] 100 clock cycles ac electrical characteristics: t a = 0c to +70c or ?40 to 85c, v dd = 5.0v 10% parameter description test condition min. typ. max. unit f in input frequency [1] out2 = ref 5 133 mhz f out output frequency out1 15-pf load [2] 10 133 mhz t r output rise time 2.0v to 0.8v, 15-pf load 2.5 ns t f output fall time 2.0v to 0.8v, 15-pf load 1.5 ns t iclkr input clock rise time [3] 10 ns t iclkf input clock fall time [3] 10 ns t pd fbin to ref skew [4, 5] measured at v dd /2 ?2 0.6 2 ns t d duty cycle 15-pf load [6, 8] 40 50 60 % t lock pll lock time power supply stable 1.0 ms t jc jitter, cycle-to-cycle fout > 30 mhz 200 ps ordering information ordering code option package name package type temperature grade w194 -70 g 8-pin soic (150-mil) commerical (0 o to 70 o c) i = industrail (?40 o to85 o c) notes: 1. input frequency is limited by output frequency range and input to output frequency multiplication factor (which is determined by circuit configuration). 2. for the higher drive -11, the load is 20 pf. 3. longer input rise and fall time will degrade skew and jitter performance. 4. all ac specifications are measured with a 50 ? transmission line, load terminated with 50 ? to 1.4v. 5. skew is measured at 1.4v on rising edges. 6. duty cycle is measured at 1.4v. 7. 33 mhz reference input suddenly stopped (0mhz). number of cycles provided prior to output falling to <16 mhz. 8. duty cycle measured at 120 mhz. for 133 mhz, degrades to 35/65 worst case.
w194 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagram 8-pin small outlined integrated circuit (soic, 150-mil)
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